J-Link debug probes are essential tools for embedded systems development. Understanding the J-Link pinout is crucial for establishing a successful connection with your target hardware. This comprehensive guide provides detailed information on the 20-pin J-Link connector, covering various interfaces including JTAG, SWD, SPI, and QSPI.
JTAG Pinout
The J-Link’s 20-pin connector supports the standard JTAG interface, compatible with ARM’s Multi-ICE. This interface utilizes a 20-way IDC (Insulation Displacement Connector) with a 2.54mm male header. Each pin serves a specific function in the JTAG communication protocol:
| Pin | Signal | Type | Description |
|---|---|---|---|
| 1 | VTref | Input | Target reference voltage; used for power detection and logic level adjustments. Connect to target VDD. |
| 2 | Not connected | NC | Leave unconnected. |
| 3 | nTRST | Output | JTAG Reset signal; active low. Connects to target nTRST. |
| 4 | GND | Ground | Connect to target ground. |
| 5 | TDI | Output | Test Data In; sends data to the target. |
| 6 | GND | Ground | Connect to target ground. |
| 7 | TMS | Output | Test Mode Select; controls the JTAG state machine. |
| 8 | GND | Ground | Connect to target ground. |
| 9 | TCK | Output | Test Clock; provides the clock signal for JTAG communication. |
| 10 | GND | Ground | Connect to target ground. |
| 11 | RTCK | Input | Return Test Clock; optional for adaptive clocking. Connect to target RTCK or ground. |
| 12 | GND | Ground | Connect to target ground. |
| 13 | TDO | Input | Test Data Out; receives data from the target. |
| 14 | Res | Reserved | Reserved for future use; can be left unconnected or connected to ground. |
| 15 | nRESET | I/O | Target reset signal; active low. Connects to target nRESET. |
| 16 | Res | Reserved | Reserved for future use; can be left unconnected or connected to ground. |
| 17 | DBGRQ | NC | Not connected in J-Link. |
| 18 | Res | Reserved | Reserved for future use; can be left unconnected or connected to ground. |
| 19 | 5V-Supply | Output | Can provide power to the target (check J-Link model capabilities). |
| 20 | Res | Reserved | Reserved for future use; can be left unconnected or connected to ground. |
SWD Pinout
J-Link also supports Serial Wire Debug (SWD), a two-wire interface offering a smaller footprint than JTAG. The SWD pinout on the 20-pin connector is as follows:
| Pin | Signal | Description |
|---|---|---|
| 1 | VTref | Target reference voltage. |
| 7 | SWDIO | Bi-directional data line. |
| 9 | SWCLK | Clock line. |
| 13 | SWO | Serial Wire Output (optional). |
| 15 | nRESET | Target reset. |
| Other Pins | As described in the JTAG pinout table (e.g., GND, VTref, nRESET). Many are NC (Not Connected) for SWD operation. |
Other Interface Pinouts (SPI, QSPI, SWD+VCOM)
The J-Link 20-pin connector can also be used for SPI, QSPI, and SWD with a Virtual COM Port (VCOM). Refer to the J-Link documentation for detailed pin assignments for these interfaces. Images of these pinouts were included in the original article.
Conclusion
Knowing the J-Link pinout is fundamental for debugging and programming embedded systems. This guide provides a clear overview of the pin assignments for common interfaces like JTAG and SWD. Always consult the official J-Link documentation and your target device’s datasheet for the most accurate and up-to-date information. SEGGER provides a variety of adapters for the J-Link 20-pin connector to facilitate various connection scenarios.
