Flashing an FPGA involves transferring a compiled design file into its non-volatile memory (NVM) for persistent configuration at power-up. This process requires converting the design into a specific Flash File Type compatible with the target FPGA and its configuration scheme. This article outlines a practical example of generating a flash file for a Stratix 10 FPGA, highlighting potential issues and solutions.
From .sof to .flash: A Step-by-Step Guide
The journey from a compiled .sof file to a programmable .flash file involves several steps:
1. Converting .sof to .rpd
Initially, the .sof file, generated by Quartus after successful compilation, needs to be converted into a raw programming data (.rpd) file. This conversion is achieved using the Programming File Generator within Quartus.
Crucially, the configuration mode must be set correctly. In this example, “Active Serial x4” was chosen as “AVST x16” didn’t offer .rpd as an output option. The input .sof, verified to work with direct programming via Quartus Programmer, is selected:
Upon successful generation, the .rpd file is created in the designated location.
2. Converting .rpd to .flash
The next step involves converting the .rpd file into the final flash file type (.flash) using the Nios II command-line tool “quartus_cpf.” Interestingly, this conversion failed within the Nios II command shell, reporting a “file not found” error:
However, executing the identical command within the Windows command shell, ensuring consistent directory paths, successfully generated the .flash file:
3. Uploading the .flash File via the Board Update Portal
With the .flash file created, the Stratix 10 board was configured to boot from the factory image using SW3.3:
This allows accessing the Board Update Portal via a web browser:
The generated .flash file is selected for upload:
The upload process is initiated and confirmed upon completion:
4. Verification and Troubleshooting
Despite the successful upload, configuring the board to boot from the user design using SW3.3 resulted in a configuration error, indicated by a red LED:
Further investigation, including adjusting MSEL settings (SW1), did not resolve the issue. This highlights the complexity of generating and utilizing the correct flash file type for FPGA configuration.
Conclusion
Generating the correct flash file type is critical for successful FPGA configuration. This article demonstrated the process, highlighting the importance of correct tool usage, configuration settings, and potential troubleshooting steps. The encountered error underscores the need for clear documentation and further investigation to ensure reliable FPGA programming.
