CAS (Column Address Strobe) is a crucial control signal in Dynamic Random Access Memory (DRAM). It works in conjunction with RAS (Row Address Strobe) to allow efficient access to data stored within the memory chip. Utilizing a multiplexed address bus, DRAM reduces the number of physical address lines required, leading to higher density memory chips.
In standard page mode DRAM, accessing data involves a two-step process using RAS and CAS. Initially, both RAS and CAS are held high. When a memory location needs to be accessed, RAS is pulled low first. This action latches the lower address bits onto the address bus, effectively selecting a specific row of memory cells for access. This initial step also triggers the refresh of the selected row, a vital process for maintaining data integrity in DRAM.
Following a short delay, typically around 30 nanoseconds, the higher address bits are applied to the same address bus, and CAS is pulled low while RAS remains low. This precise timing sequence allows the column address to be latched, pinpointing the exact memory cell within the previously selected row. The actual data read or write operation occurs at this point. Other control signals, such as Output Enable (OE) and Chip Select (CS), along with the Write Enable (!WE) signal and data lines, function similarly to how they operate in Static RAM (SRAM).
Once the read or write operation is complete, both RAS and CAS return to their high state, concluding the memory access cycle. When the DRAM isn’t actively being accessed, refresh cycles occur. During these cycles, RAS is pulsed low, and the address lines specify which row to refresh. A binary counter often drives the address lines during refresh, ensuring all rows are periodically refreshed.
This intricate dance between RAS and CAS, along with the address bus and other control signals, allows for efficient data access in the densely packed memory cells of DRAM. This efficiency is key to the performance of modern computer systems. For a more detailed understanding of DRAM operation, including various access modes like fast page mode and those employed by EDO DRAM, refer to the linked document below.
